1. Technical Field
The present invention relates to circuits and circuit designs, and in particular to circuits which account for inter-die and intra-die variations.
2. Description of the Related Art
As the technology scales, inter-die and intra-die variations in process parameters (e.g., channel length (L), width (W), threshold voltage (Vt), etc.) have become serious problems in circuit design. The device-to-device (intra-die) variations in L, W or Vt between the neighboring transistors in an SRAM cell can significantly degrade not only stability of the cell but read and write delays. This causes minimum voltage conditions for read and write operations as the PFET threshold voltage degrades due to the negative bias temperature instability (NBTI) effect after burn-in.
If the PFET is made too strong then the “write margin” degrades significantly. To alleviate these problems and minimize the half select (unselected cells on the selected wordline) situation, new circuits and design techniques are needed.